The development of electrically erasable programmable read-only memories (EEPROMs) has made possible a non-volatile memory which can be altered by electrically programming the device. A conventional requirement of prior types of read-only memories was a transparent window on the chip for exposing the memory cells to ultraviolet light for erasing the cell contents prior to reprogramming. With current read-only memories which are electrically erasable, both the erasing and programming can be accomplished employing electrical signals, thereby allowing the devices to remain connected in the circuit, as well as alleviating the need for ultraviolet light sources.
In an effort to reduce the wafer area of EEPROM memory cells so that more field effect transistor cells can be fabricated on a single integrated circuit chip, recent developments have reduced the memory cell from a four-transistor configuration to two transistors. In the two-transistor EEPROM cell arrangement, one field effect transistor provides the non-volatile storage mechanism for electrical charge, while the other transistor provides electrical isolation of the storage transistor from a bit line of the memory array. The isolation transistor is necessary as the storage transistor may be transformed into a depletion mode device during electrical erasing, thereby rendering it leaky or unable to be placed in a nonconductive state.
The two-transistor EEPROM cell has been further refined to integrate the storage and isolation functions into a single transistor cell, such transistor providing both functions. The technical article "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device", by T. Y. Chan, K. K. Young & C. Hu, Electronics Research Laboratory, Department of Electrical Engineering & Computer Sciences, University of California, Berkley, 1986, describes such an EEPROM cell.
While the EEPROM memory cell of the noted technical article enables further reduction of the cell area, and thus an integration of more cells on a chip, the disadvantage attendant with such a technique is that separate source and drain diffusions are required for each cell, as well as one or more metal contacts for gaining access to each cell by word and bit lines. Hence, in addition to requiring more complicated mask and fabrication steps, and the resulting yield and reliability problems, such a memory cell is suboptimal in terms of wafer area requirements.
From the foregoing, it can be seen that a need exists for a non-volatile EEPROM memory cell which employs a single transistor arrangement for electrically erasing and programming data therein, and which requires a smaller wafer area per cell than EEPROM devices heretofore known. An associated need exists for an EEPROM memory cell which is easily manufacturable, requires only a small wafer area, and can be fabricated utilizing presently known silicon fabrication techniques and facilities.